1. Technical Field
The present invention broadly relates to reliability testing of semiconductor devices and, particularly to an alternating current (AC) stress test circuit for hot carrier injection (HCI) degradation evaluation, a method for evaluating/predicting AC stress induced HCI degradation and a test structure for HCI degradation evaluation in semiconductor devices.
2. Description of the Related Art
In the course of enhancing semiconductor device design and performance, faster circuit operation has been achieved with the reduction of transistor sizes. For designers, attempts to continue to improve device performance face increasing challenges as further reductions in transistor sizes are sought. For example, it is commonly known that a problem with hot carrier injection increases as device sizes shrink.
Hot carrier injection (HCI) occurs as a result of the reduced channel size of sub-micron transistors causing an increase in the electric field, which can allow the carrier to be injected into the gate dielectric of the transistor. Over time, the resulting charged gate dielectric causes device degradation, raising the threshold voltage and reducing the transconductance. Device testing attempts to determine the rate of degradation due to HCI.
Conventionally, an AC to DC (AC/DC) conversion factor is used to express the rate of HCI degradation in semiconductor devices. A traditional approach for getting the AC/DC conversion factor involves the use of an inverter ring oscillator for investigation of dynamic (AC) stress induced HCI degradation and the use of a single device for investigation of static (DC) stress induced HCI degradation. In particular, higher stress-voltages are forced in the inverter ring oscillator to get AC frequency degradation at 1.1 Vcc, and higher stress-voltages are forced in the single device to get DC Idsat (i.e., drain saturated drain current) degradation at 1.1 Vcc, wherein Vcc is a power supply voltage. Thereafter, the AC/DC conversion factor is determined by a ratio of a lifetime of M % frequency change during ring oscillator stressing (i.e., AC stressing) to another lifetime of 10% Idsat change during DC stressing, wherein M % is set to be 2.5% for nMOS device or else is set to be 5% for pMOS device.
In fact, a definition of the AC/DC conversion factor is a ratio of time to failure (TTF)@AC Idsat 10% degradation to TTF@DC Idsat 10% degradation, where the TTF@AC Idsat 10% degradation represents a lifetime of 10% Idsat change during AC stressing, and the TTF@DC Idsat 10% degradation represents a lifetime of 10% Idsat change during DC stressing.
Accordingly, it is found that the traditional approach to get AC Idsat degradation by simulation then using it as a medium to get the correlation between AC frequency degradation and DC Idsat degradation for the purpose of maintaining realistic AC stress waveforms, rather than directly get AC Idsat degradation during ring oscillator stressing. Unfortunately, the accuracy for determining the AC/DC conversion factor by the traditional approach is not satisfactory and thus there is a need for increasing accuracy in evaluating HCI degradation in semiconductor devices.